1. Field of the Invention
The invention relates to an output buffer circuit mounted on a semiconductor integrated circuit device, and converting logic data having been processed in the semiconductor integrated circuit device, into a logic signal, and outputting outwardly of the semiconductor integrated circuit device, and more particularly to such an output buffer circuit having a function of carrying out pre-emphasis in accordance with attenuation in a transmission line.
2. Description of the Related Art
Some of output buffer circuits for transmitting a logic signal to a transmission line acting as a distributed parameter circuit are designed to have a so-called pre-emphasis function by which a signal waveform is emphasized in accordance with attenuation in a signal on a transmission line. Such output buffer circuits are accomplished generally by a current-mode type circuit, that is, a circuit which deals with a signal indicative of a current.
The current-mode type circuit is accompanied with a problem that its structure causes the circuit to work not so well at a relatively low voltage.
However, as a technique for fabricating a semiconductor integrated circuit in a smaller scale has been developed, a semiconductor integrated circuit can work with lower power consumption because of reduction in an operational voltage. As a result, a semiconductor integrated circuit is presently requested to operate at a high rate at a lower voltage.
Japanese Unexamined Patent Publication No. 2000-68816 which is based on German patent application No. 19825258.7 filed on Jun. 5, 1998, for instance, has suggested an output buffer circuit to meet such a request.
The output buffer circuit suggested in the Publication is comprised of an output stage illustrated in FIG. 1, and a control circuit (not illustrated). The output stage illustrated in FIG. 1 is comprised of n-channel field effect transistors N11, N13 and N15 each electrically connected between a higher voltage source VDD and an output terminal TOUT, n-channel field effect transistors N12, N14 and N16 each electrically connected between a lower voltage source VSS and the output terminal TOUT, and inverters INV 11, INV 12 and INV 13. The n-channel field effect transistors N11, N13 and N15 define a first impedance circuit, and the n-channel field effect transistors N12, N14 and N16 define a second impedance circuit.
The inverters INV 11, INV 12 and INV 13 receive control signals A1, A2 and A3, and inverted those control signals A1, A2 and A3. The control signals A1, A2 and A3 are applied to gate electrodes of the n-channel field effect transistors N11, N13 and N15, and the controls signals A1, A2 and A3 having been inverted by the inverters INV 11, INV 12 and INV 13 are applied to gate electrodes of the n-channel field effect transistors N12, N14 and N16. The n-channel field effect transistors N11, N13, N15, N12, N14 and N16 in the first and second impedance circuits are turned on or off such that an impedance ratio of an impedance of the first impedance circuit to an impedance of the second impedance circuit is equal to any one of at least three different values and that a sum of conductances of the first and second impedance circuits is not dependent on the impedance ratio. This ensures that an output impedance is kept almost equal to a predetermined value regardless of pre-emphasis.
Though the above-mentioned output buffer circuit can operate at a lower voltage than a voltage at which a general current-mode type circuit can operate, the output buffer circuit has to include the control circuit for controlling on/off of the field effect transistors constituting the first and second impedance circuits. The control circuit transmits the control signals A1, A2 and A3 required for a pre-emphasis step, by conducting logic operations such as logical product (AND) and logical sum (OR) through the use of data to be transmitted. As a result, the output buffer circuit unavoidably has much propagation delay time from an input to an output. An output signal is influenced by voltage source noises and voltage fluctuation during the propagation delay time, and thus, jitter is increased, resulting in that the output buffer circuit cannot operate at a high rate.
Japanese Unexamined Patent Publication No. 11-345054 has suggested a driver circuit for transmitting signals, including an output stage driver, a previous stage driver for driving the output stage driver, and a level adjuster for adjusting an output level of the previous stage driver. The output stage driver transmits a variable-level signal in accordance with the output level of the previous stage driver.
Japanese Unexamined Patent Publication No. 5-344026 has suggested a pre-emphasis circuit including an amplifying circuit equipped with a negative feed-back circuit which provided a smaller feed-back in response to a higher frequency.
Japanese Unexamined Patent Publication No. 7-183746 has suggested (a) an emphasis/de-emphasis circuit including an operational amplifier in which a de-emphasized signal input is input to a non-inverted input terminal, (b) a switching circuit having an input electrically connected to an output terminal of the operational amplifier, another input electrically connected to an emphasis input, and an output electrically connected to a de-emphasis signal output terminal, and equalizing the input and output to each other with respect to a voltage, selecting one of the input and another input, and transmitting the selected input, and (c) an emphasis circuit having an input electrically connected to an output of the switching circuit, and an output electrically connected to both the non-inverted input terminal of the operational amplifier and an emphasis signal output terminal, and conducting an emphasis step to signals received through the input. By means of the switching circuit, an emphasis step or a deemphasis step is carried out.
Japanese Unexamined Patent Publication No. 9-139664, which is based on United Kingdom patent application No. 9518183.0 filed on Sep. 6, 1995, has suggested an integrated circuit including a driver circuit which transmits data signals to communication channels. The driver circuit is comprised of a first output buffer including a plurality of pull-up transistors electrically connected to a first output conductor through pull-up resistors, and a plurality of pull-down transistors electrically connected to the first output conductor through pull-down resistors, a plurality of delay circuits each transmitting a delay data signal to each of control terminals of the pull-up and pull-down transistors, and control circuits operating one of the delay circuits selected in accordance with a data input signal.
Japanese Patent No. 2781137 (Japanese Unexamined Patent Publication No. 6-350961) has suggested a digital non-linear pre-emphasis circuit including a first filter which varies a gain in an input digital signal in accordance with an amplitude of a high frequency band of the input digital signal, and transmits a signal having the varied gain, a second filter which varies a band at which the signal output from the first filter can pass, in accordance with an amplitude of the signal output from the first filter, and a mixer which mixes the input digital signal with a signal output from the second filter, and transmits a pre-emphasized signal in which a high frequency band of the input signal is emphasized.
In view of the above-mentioned problems in the conventional output buffer circuit, it is an object of the present invention to provide an output buffer circuit which is capable of operating at a relatively low voltage in spite of having a function of pre-emphasis, and which has a shortened propagation delay time from an input to an output thereof.
There is provided an output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, including (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line, the second buffer having an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved.
It is preferable that the second buffer is comprised of one or more tri-state type buffer(s) which is (are) activated or inactivated in accordance with whether a pre-emphasis step is to be carried out or not.
For instance, the first buffer may be comprised of (a1) a first p-channel field effect transistor having a current path between a higher voltage source and an output terminal, and having a gate electrode electrically connected to a first input terminal, and (a2) a first n-channel field effect transistor having a current path between a lower voltage source and the output terminal, and having a gate electrode electrically connected to the first input terminal, the second buffer may be comprised of (b1) a second p-channel field effect transistor having a current path between the higher voltage source and the output terminal, and having a gate electrode electrically connected to a second input terminal, and (b2) a second n-channel field effect transistor having a current path between the lower voltage source and the output terminal, and having a gate electrode electrically connected to the second input terminal, the first p-channel field effect transistor may have a driving capacity higher than a driving capacity of the second n-channel field effect transistor, and the first n-channel field effect transistor may have a driving capacity higher than a driving capacity of the second p-channel field effect transistor.
It is preferable that the second logic signal has a logical value different from a logical value of a logic signal transmitted from the first buffer at latest when the first logic signal is transited.
It is preferable that the transmission line is terminated with a terminated resistor electrically connected to a terminating voltage source.
It is preferable that the transmission line is terminated with a first terminated resistor electrically connected to a higher voltage source, and a second terminated resistor electrically connected to a lower voltage source.
It is preferable that an output impedance of the first buffer is matched to a characteristic impedance of the transmission line.
It is preferable that the second buffer is activated when a logic signal in the transmission line is attenuated in a higher degree and hence a pre-emphasis step is to be carried out, and is inactivated when the logic signal is attenuated in a lower degree and hence a pre-emphasis step is not to be carried out.
It is preferable that the second buffer is inactivated while a test is being conducted.
There is further provided an output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, including (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line, wherein the second buffer has an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved, the first buffer is comprised of (a1) a first p-channel field effect transistor having a current path between a higher voltage source and an output terminal, and having a gate electrode electrically connected to a first input terminal, and (a2) a first n-channel field effect transistor having a current path between a lower voltage source and the output terminal, and having a gate electrode electrically connected to the first input terminal, the second buffer is comprised of a tri-state type buffer including (b1) a second p-channel field effect transistor having a current path between the higher voltage source and the output terminal, and having a gate electrode electrically connected to a second input terminal, (b2) a second n-channel field effect transistor having a current path between the lower voltage source and the output terminal, and having a gate electrode electrically connected to the second input terminal, (b3) a third p-channel field effect transistor electrically connected in series with the second p-channel field effect transistor, and turned on or off in accordance with whether a pre-emphasis step is to be carried out or not, and (b4) a third n-channel field effect transistor electrically connected in series with the second n-channel field effect transistor, and turned on or off simultaneously with the third p-channel field effect transistor, the first p-channel field effect transistor having a driving capacity higher than a sum of driving capacities of the second and third n-channel field effect transistors, and the first n-channel field effect transistor having a driving capacity higher than a sum of driving capacities of the second and third p-channel field effect transistors.
There is still further provided an output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, including (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line, wherein the second buffer has an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved, the first buffer is comprised of (a1) a first p-channel field effect transistor having a current path between a higher voltage source and an output terminal, and having a gate electrode electrically connected to a first input terminal, and (a2) a first n-channel field effect transistor having a current path between a lower voltage source and the output terminal, and having a gate electrode electrically connected to the first input terminal, the second buffer is comprised of first to N-th tri-state type buffers each including (b1) a second p-channel field effect transistor having a current path between the higher voltage source and the output terminal, and having a gate electrode electrically connected to a second input terminal, (b2) a second n-channel field effect transistor having a current path between the lower voltage source and the output terminal, and having a gate electrode electrically connected to the second input terminal, (b3) a third p-channel field effect transistor electrically connected in series with the second p-channel field effect transistor, and turned on or off in accordance with whether a pre-emphasis step is to be carried out or not, and (b4) a third n-channel field effect transistor electrically connected in series with the second n-channel field effect transistor, and turned on or off simultaneously with the third p-channel field effect transistor, wherein N is an integer equal to or greater than 2, the first p-channel field effect transistor has a driving capacity higher than a sum of driving capacities of the second and third n-channel field effect transistors in the first to N-th tri-state type buffers, and the first n-channel field effect transistor has a driving capacity higher than a sum of driving capacities of the second and third p-channel field effect transistors in the first to N-th tri-state type buffers.
It is preferable that a M-th tri-state type buffer has a driving capacity equal to about a half of a driving capacity of a (Mxe2x88x921)-th tri-state type buffer, wherein M is an integer equal to or smaller than N.
It is preferable that the first to N-th tri-state type buffers are activated or inactivated in accordance with a binary code indicating pre-emphasis.
It is preferable that the first to N-th tri-state type buffers are activated or inactivated in accordance with attenuation of the transmission line.
It is preferable that the second buffer is activated such that pre-emphasis is minimized in a test.
Hereinbelow is explained an operation of the output buffer circuit in accordance with the present invention.
The output buffer circuit receives a first logic signal through a first input terminal which first logic signal corresponds to a signal series to be transmitted, and further receives a second logic signal through a second input terminal which second logic signal has a predetermined logical relation with the first logic signal. For instance, the second logic signal may be comprised of a signal series obtained by delaying the first logic signal to be transmitted, by one bit and inverting the same. The second buffer cooperates with the first buffer to drive a transmission line.
For instance, when the first and second logic signals have the same logical value, the first and second buffers transmit logic signals having the same logical value. Since an output impedance of the second buffer is designed so as to improve attenuation in a signal on the transmission line, the output impedance of the output buffer circuit is apparently reduced, that is, a driving capacity of the output buffer circuit is enhanced, resulting in that the output buffer circuit transmits a logic signal having an emphasized voltage (for instance, Voh 1 and Vol 1 illustrated in FIG. 3).
For another instance, when the first and second signals have different logical values from each other, the second buffer transmits a logic signal having a logical value opposite to a logical value of a logic signal to be transmitted from the first buffer. Since an output impedance of the second buffer is set higher than an output impedance of the first buffer, a logical value of a logic signal transmitted from the first buffer is kept as it is. Thus, an output impedance of the output buffer circuit is apparently increased, that is, a driving capacity of the output buffer circuit is apparently reduced, resulting in that the output buffer circuit transmits a logic signal having a de-emphasized voltage (for instance, Voh 2 and Vol 2 illustrated in FIG. 3).
As mentioned above, if a logical value of the first logic signal to be transmitted varies, a waveform of a logic signal to be transmitted is emphasized, whereas if a logical value of the first logic signal does not vary, or is kept as it is, the waveform is not emphasized, or is de-emphasized. This results in that a voltage of a logic signal to be transmitted to a transmission line becomes close to a logic threshold voltage (VTT) in preparation for next variance in a logic signal.
Accordingly, the present invention provides an advantage that high frequency components in a waveform of the first logic signal to be transmitted are reinforced, and an improvement is obtained in so-called eye pattern in a waveform of a signal received after having passed a transmission line with high loss, that is, a long or thin transmission line, such as a cable or wiring of a plent substrate. Hence, the present invention makes it possible to transmit a signal at a higher rate through a smaller-diameter cable by a longer distance than an output buffer circuit having no pre-emphasis function.
In addition, since the output buffer circuit in accordance with the present invention is designed to have a CMOS type circuit structure, the output buffer can operate at a lower source voltage than a voltage at which a current-mode type circuit operates.
Furthermore, since it is not necessary to conduct logical operation such as logical product (AND) and logical sum (OR) to received signals such as the first and second logic signals when a pre-emphasis step is to be carried out, it would be possible to shorten propagation delay time from an input section to an output section, ensuring an operation at a higher rate.